Design Verification Engineer

Position: Design Verification Engineer – Senior

Location: Ottawa, ON

Duration: 12 Months

Job Type: Contract

Work Type: Onsite

Key Responsibilities:

Develop/Maintain tests for functional verification with UVM verification at the subsystem level

Build testbench components to support the next generation IP

Maintain or improve current test libraries to support IP level testing

Technically lead IPs in Control Fabric,

Have exposure to AXI protocol and Bootcode Verification

Provide technical support to other teams

Preferred Experience:

5+ years’ experience required

Good at C/C++

Good at SV and UVM

Good scripting knowledge in Perl, Ruby and Makefile

Familiarity with System Verilog and modern verification libraries like UVM

Academic Credentials:

Bachelors (required) or Masters degree in computer engineering/Electrical Engineering

Top priority skills:

UVM , system Verilog , C and C++