Senior CAD Engineer

Job Description

<p><p>6 days ago Be among the first 25 applicants</p>
<p>This range is provided by PHIZENIX. Your actual pay will be based on your skills and experience — talk with your recruiter to learn more.</p>
<h3>Base pay range</h3>
<p>$170,000.00/yr - $215,000.00/yr</p>
<p>Direct message the job poster from PHIZENIX</p>
<p>We’re looking for an experienced <b>CAD Engineer</b> to develop, enhance, and support advanced <b>EDA environments and design automation flows</b> for next‑generation semiconductor development. In this role, you will serve as the technical bridge between <b>Analog/AMS and Digital/ASIC Verification teams</b>, ensuring smooth integration from schematic capture through signoff. You will own <b>PDK integration, flow automation, compute resource optimization, and mixed‑signal verification infrastructure</b>, working closely with design engineers, IT teams, and EDA vendors to drive efficiency and silicon success.</p>
<h3>Key Responsibilities</h3>
<ul>
<li>Develop, maintain, and optimize <b>CAD and EDA environments</b> for Analog/AMS, ASIC, Photonics, and Systems teams to ensure seamless integration and productivity.</li>
<li>Define, implement, and automate <b>design and signoff flows</b> for custom and digital design environments.</li>
<li>Install, configure, and manage <b>EDA tools</b> (Cadence, Synopsys, Siemens) and <b>FlexLM license servers</b>.</li>
<li>Integrate and validate <b>PDKs, technology files, and IP libraries</b>, collaborating with foundries and third‑party vendors.</li>
<li>Oversee <b>SLURM cluster infrastructure</b>, including job scheduling and resource allocation to improve throughput and ROI.</li>
<li>Develop automation scripts using <b>Python, TCL, SKILL, and Bash</b> to streamline CAD flows and minimize manual effort.</li>
<li>Manage <b>design repositories</b> (Git, IC Manage) and enforce best practices for version control and configuration management.</li>
<li>Troubleshoot and optimize <b>SPICE, DRC/LVS, PEX, and EMIR</b> issues, supporting design teams for higher performance and reliability.</li>
<li>Monitor <b>license utilization and compute resource metrics</b>, recommending strategies for cost‑effective scalability.</li>
<li>Collaborate with <b>EDA vendors</b> to resolve tool issues, influence feature development, and assess new technologies.</li>
</ul>
<h3>Qualifications</h3>
<ul>
<li>Bachelor’s or master’s degree in electrical engineering or computer science.</li>
<li><b>8+ years</b> of hands‑on experience in <b>CAD/EDA design automation</b>, supporting analog/AMS and digital verification environments.</li>
<li>Strong expertise with <b>Cadence Virtuoso, ADE Assembler/Explorer, and Spectre</b> simulation environments.</li>
<li>Experience with <b>signoff tools</b> such as Pegasus, Quantus, and VoltusFI (or equivalent Calibre suites).</li>
<li>Proficiency in <b>SKILL and Python scripting</b> for design automation and productivity improvements.</li>
<li>Experience managing <b>FlexLM license servers</b>, including installation, configuration, and troubleshooting.</li>
<li>Hands‑on experience with <b>PDK integration for advanced FinFET nodes (e.g., TSMC N5)</b>.</li>
<li>Proficiency with <b>version control systems</b> such as Git or IC Manage (gdpxl).</li>
</ul>
<h3>Preferred Qualifications</h3>
<ul>
<li>Experience with <b>Virtuoso AMS Designer</b> and <b>Cadence Xcelium</b> for mixed‑signal simulation and behavioral modeling.</li>
<li>Familiarity with <b>SLURM cluster management</b> and high‑performance computing environments.</li>
<li>Understanding of <b>Digital RTL‑to‑GDSII flows</b>, including synthesis, P&R, STA, and PV.</li>
<li>Exposure to <b>CI/CD pipelines</b> for CAD flow release automation and regression testing.</li>
<li>Strong written and verbal communication skills with proven ability to <b>mentor junior engineers</b>.</li>
</ul>
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