Virtualization Domain Systems Design Engineer

Job Description

<p><p><b>WHAT YOU DO AT AMD CHANGES EVERYTHING</b></p>
<p>At AMD, our mission is to build great products that accelerate next‑generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond.</p>
<p><b>Together, we advance your career.</b></p>
<p><b>THE ROLE:</b></p>
<p>The AMD Platform Validation Team is looking for an energetic IP Systems Engineer to join our growing team. As a key contributor, you will help drive and enhance AMD’s ability to deliver the highest quality, industry‑leading technologies to market.</p>
<p><b>THE PERSON:</b></p>
<p>Dynamic self‑starter with a passion for improving and innovating. As a Systems Engineer, you will drive the planning, verification, and debug of virtualization IPs for AMD dGPU and APU programs.</p>
<p><b>KEY RESPONSIBILITIES:</b></p>
<ul>
<li>Define and execute the overall functional test plan and verification strategy for virtualization IPs.</li>
<li>Drive technical innovation to enhance AMD’s capabilities in validation/verification, including tool and script development, methodology enhancement, and internal cross‑functional initiatives.</li>
<li>Debug issues found during pre‑silicon, bring‑up, validation, and production phases of SOC programs.</li>
<li>Work closely with design, diagnostics, emulation, firmware, and driver teams to ensure readiness for first silicon arrival, enablement of functionality, and debug of critical features.</li>
<li>Engage in pre‑silicon verification efforts, including FPGA‑based emulation, DV, and other software/hardware modeling frameworks.</li>
<li>Lead collaborative technical discussions to drive resolution on technical issues and roll out initiatives.</li>
<li>Develop knowledge of system architecture/debug and other IPs.</li>
<li>Support issues on customer platforms as requested by customer support teams.</li>
</ul>
<p><b>PREFERRED EXPERIENCE:</b></p>
<ul>
<li>Programming/scripting skills (e.g. C/C++, Perl, Ruby, Python).</li>
<li>Experience with ASIC debug techniques and methodologies.</li>
<li>Experience with common lab equipment, including protocol/logic analyzers, oscilloscopes, etc.</li>
<li>Experience with board/platform‑level debug, including delivery, sequencing, analysis, and optimization.</li>
<li>Knowledge of physical and protocol levels of common high‑speed interfaces an asset.</li>
<li>In‑depth knowledge of PC architectures an asset.</li>
<li>Excellent written and verbal communication skills.</li>
<li>Dynamic team working environment.</li>
<li>Leadership and mentoring skills a definite asset.</li>
<li>Self‑starter able to independently drive tasks to completion.</li>
<li>Ability to be flexible in terms of responsibilities.</li>
</ul>
<p><b>ACADEMIC CREDENTIALS:</b></p>
<ul>
<li>Bachelor’s or Master’s degree in electrical or computer engineering.</li>
</ul>
<p><b>#LI‑LB1</b></p>
<p>Benefits offered are described: AMD benefits at a glance.</p>
<p>AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee‑based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third‑party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.</p></p>
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